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a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 1 240pin ddr3 sdram unbeffered dimm * hynix semiconductor reserves the right to change products or specific ations without notice. ddr3 sdram unbuffered dimms based on 2gb b-die hmt312u6bfr6c hmt325u6bfr8c hmt325u7bfr8c hmt351u6bfr8c hmt351u7bfr8c b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 2 revision history revision no. history draft date remark 0.1 initial release dec. 2009 0.2 added idd specification feb. 2010 0.3 editorial change apr. 2010 1.0 dimm line-up(1rx16) added oct. 2010 b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 3 description hynix unbuffered ddr3 sdram dimms (unbuffered doub le data rate synchronous dram dual in-line memory modules) are low power, high-speed oper ation memory modules that use hynix ddr3 sdram devices. these unbuffered sdram dimms are intended for use as main memory when installed in systems such as pcs and workstations. feature ? vdd=1.5v +/- 0.075v ? vddq=1.5v +/- 0.075v ? vddspd=3.0v to 3.6v ? functionality and operations comply with the ddr3 sdram datasheet ? 8 internal banks ? data transfer rates: pc3-10600, pc3-8500, or pc3-6400 ? bi-directional differential data strobe ? 8 bit pre-fetch ? burst length (bl) switch on-the-fly: bl 8 or bc (burst chop) 4 ? supports ecc error correction and detection ? on die termination (odt) supported ? temperature sensor with integrated spd (serial presence detect) eeprom ? rohs compliant * this product is in compliance with the rohs directive. ordering information part number density organization component composition # of ranks fdhs hmt312u6bfr6c-g7/h9/pb 1gb 128m x64 128mx16(h5tq2g63bfr)*4 1 x hmt325u6bfr8c-g7/h9/pb 2gb 256m x64 256mx8(h5tq2g83bfr)*8 1 x hmt325u7bfr8c-g7/h9/pb 2gb 256m x72 256mx8(h5tq2g83bfr)*9 1 x HMT351U6BFR8C-G7/h9/pb 4gb 512mx64 256mx8(h5tq2g83bfr)*16 2 x hmt351u7bfr8c-g7/h9/pb 4gb 512mx72 256mx8(h5tq2g83bfr)*18 2 x b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 4 key parameters speed grade address table mt/s grade tck (ns) cas latency (tck) trcd (ns) trp (ns) tras (ns) trc (ns) cl-trcd-trp ddr3-1066 -g7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 ddr3-1333 -h9 1.5 9 13.5 13.5 36 49.5 9-9-9 ddr3-1600 -pb 1.25 11 13.75 13.75 35 48.75 11-11-11 grade frequency [mhz] remark cl6 cl7 cl8 cl9 cl10 cl11 -g7 800 1066 1066 -h9 800 1066 1066 1333 1333 -pb 800 1066 1066 1333 1333 1600 1gb(1rx16) 2gb(1rx8) 2gb(1rx8) 4gb(2rx8) 4gb(2rx8) refresh method 8k/64ms 8k/64ms 8k/64ms 8k/64ms 8k/64ms row address a0-a13 a0-a14 a0-a14 a0-a14 a0-a14 column address a0-a9 a0-a9 a0-a9 a0-a9 a0-a9 bank address ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 page size 2kb 1kb 1kb 1kb 1kb b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 5 pin descriptions pin name description pin name description a0?a15 sdram address bus scl i 2 c serial bus clock for eeprom ba0?ba2 sdram bank select sda i 2 c serial bus data line for eeprom ras sdram row address strobe sa0?sa2 i 2 c slave address select for eeprom cas sdram column address strobe v dd * sdram core power supply we sdram write enable v dd q * sdram i/o driver power supply s 0?s 1 dimm rank select lines v ref dq sdram i/o reference supply cke0?cke1 sdram clock enable lines v ref ca sdram command/address reference supply odt0?odt1 on-die termination control lines v ss power supply return (ground) dq0?dq63 dimm memory data bus v ddspd serial eeprom positive power supply cb0?cb7 dimm ecc check bits nc spare pins (no connect) dqs0?dqs8 sdram data strobes (positive line of differential pair) test memory bus analysis tools (unused on memory dimms) dqs 0?dqs 8 sdram data strobes (negative line of differential pair) reset set drams to known state dm0?dm8 sdram data masks/high data strobes (x8-based x72 dimms) v tt sdram i/o termination supply ck0?ck1 sdram clocks (positive line of differential pair) rsvd reserved for future use ck 0?ck 1 sdram clocks (negative line of differential pair) - - *the v dd and v dd q pins are tied common to a sing le power-plane on these designs b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 6 input/output functional descriptions symbol type polarity function ck0?ck1 ck 0?ck 1 sstl differential crossing ck and ck are differential clock inputs. all the ddr3 sdram addr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is referenc e to the crossing of ck and ck (both directions of crossing). cke0?cke1 sstl active high activates the sdram ck si gnal when high and deac tivates the ck signal when low. by deactivating the cloc ks, cke low initiates the power down mode, or the self refresh mode. s 0?s 1sstlactive low enables the associated sdram command decoder when low and disables the command decoder when high. wh en the command decoder is dis- abled, new commands are ignored but previous operations continue. this signal provides for external rank selection on systems with multiple ranks. ras , cas, we sstl active low ras , cas , and we ( along with s ) define the command being entered. odt0?odt1 sstl active high when high, termination resistance is enabled for all dq, dqs, dqs and dm pins, assuming this function is enabled in the mode register 1 (mr1). v ref dq supply reference voltage for sstl15 i/o inputs. v ref ca supply reference voltage for sstl 15 command/address inputs. v dd q supply power supply for the ddr3 sdram output buffers to provide improved noise immunity. for all current ddr3 unbuffered dimm designs, v dd q shares the same power plane as v dd pins. ba0?ba2 sstl ? selects which sdram bank of eight is activated. a0?a15 sstl ? during a bank activate command cycle, address input defines the row address (ra0?ra15). during a read or write command cycl e, address input defines the column address. in addition to the column a ddress, ap is used to invoke autopre- charge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be pre- charged. if ap is low, autoprecharge is disabled. during a precharge com- mand cycle, ap is used in conjunction with ba0, ba1, ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burs t chop (on-the-fly) will be per- formed (high, no burst ch op; low, burst chopped). dq0?dq63, cb0?cb7 sstl ? data and check bit input/output pins. dm0?dm8 sstl active high dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. alth ough dm pins are input only, the dm loading matches the dq and dqs loading. v dd , v ss supply power and ground for the ddr3 sdram input buffers, and core logic. v dd and v dd q pins are tied to v dd /v dd q planes on these modules. b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 7 pin assignments dqs0?dqs8 dqs 0?dqs 8 sstl differential crossing data strobe for input and output data. sa0?sa2 ? these signals are tied at the system planar to either v ss or v ddspd to con- figure the serial spd eeprom address range. sda ? this bidirectional pin is used to tr ansfer data into or out of the spd eeprom. an external resistor may be connected from the sda bus line to v ddspd to act as a pullup on the system board. scl ? this signal is used to clock data into and out of th e spd eeprom. an external resistor may be connec ted from the scl bus time to v ddspd to act as a pullup on the system board. v ddspd supply power supply for spd eeprom. this supply is separate from the v dd /v dd q power plane. eeprom supply is operable from 3.0v to 3.6v. front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc 1v ref dq v ref dq 121 v ss v ss 61 a2 a2 181 a1 a1 2v ss v ss 122 dq4 dq4 62 v dd v dd 182 v dd v dd 3 dq0 dq0 123 dq5 dq5 63 ck1 ck1 183 v dd v dd 4dq1 dq1124 v ss v ss 64 ck 1ck 1184 ck0 ck0 5 v ss v ss 125 dm0 dm0 65 v dd v dd 185 ck 0ck 0 6dqs 0dqs 0 126 nc nc 66 v dd v dd 186 v dd v dd 7 dqs0 dqs0 127 v ss v ss 67 v ref ca v ref ca 187 nc event 8 v ss v ss 128 dq6 dq6 68 nc nc 188 a0 a0 9 dq2 dq2 129 dq7 dq7 69 v dd v dd 189 v dd v dd 10 dq3 dq3 130 v ss v ss 70 a10 a10 190 ba1 2 ba1 2 11 v ss v ss 131 dq12 dq12 71 ba0 2 ba0 2 191 v dd v dd 12 dq8 dq8 132 dq13 dq13 72 v dd v dd 192 ras ras 13 dq9 dq9 133 v ss v ss 73 we we 193 s 0s 0 14 v ss v ss 134 dm1 dm1 74 cas cas 194 v dd v dd 15 dqs 1dqs 1 135 nc nc 75 v dd v dd 195 odt0 odt0 16 dqs1 dqs1 136 v ss v ss 76 s1 s1 196 a13 a13 nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. symbol type polarity function b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 8 17 v ss v ss 137 dq14 dq14 77 odt1 odt1 197 v dd v dd 18 dq10 dq10 138 dq15 dq15 78 v dd v dd 198 nc nc 19 dq11 dq11 139 v ss v ss 79 nc nc 199 v ss v ss 20 v ss v ss 140 dq20 dq20 80 v ss v ss 200 dq36 dq36 21 dq16 dq16 141 dq21 dq21 81 dq32 dq32 201 dq37 dq37 22 dq17 dq17 142 v ss v ss 82 dq33 dq33 202 v ss v ss 23 v ss v ss 143 dm2 dm2 83 v ss v ss 203 dm4 dm4 24 dqs 2dqs 2144 nc nc 84 dqs 4dqs 4 204 nc nc 25 dqs2 dqs2 145 v ss v ss 85 dqs4 dqs4 205 v ss v ss 26 v ss v ss 146 dq22 dq22 86 v ss v ss 206 dq38 dq38 27 dq18 dq18 147 dq23 dq23 87 dq34 dq34 207 dq39 dq39 28 dq19 dq19 148 v ss v ss 88 dq35 dq35 208 v ss v ss 29 v ss v ss 149 dq28 dq28 89 v ss v ss 209 dq44 dq44 30 dq24 dq24 150 dq29 dq29 90 dq40 dq40 210 dq45 dq45 31 dq25 dq25 151 v ss v ss 91 dq41 dq41 211 v ss v ss 32 v ss v ss 152 dm3 dm3 92 v ss v ss 212 dm5 dm5 33 dqs 3dqs 3 153 nc nc 93 dqs 5dqs 5 213 nc nc 34 dqs3 dqs3 154 v ss v ss 94 dqs5 dqs5 214 v ss v ss 35 v ss v ss 155 dq30 dq30 95 v ss v ss 215 dq46 dq46 36 dq26 dq26 156 dq31 dq31 96 dq42 dq42 216 dq47 dq47 37 dq27 dq27 157 v ss v ss 97 dq43 dq43 217 v ss v ss 38 v ss v ss 158 nc cb4 98 v ss v ss 218 dq52 dq52 39 nc cb0 159 nc cb5 99 dq48 dq48 219 dq53 dq53 40 nc cb1 160 v ss v ss 100 dq49 dq49 220 v ss v ss 41 v ss v ss 161 dm8 dm8 101 v ss v ss 221 dm6 dm6 42 nc dqs 8 162 nc nc 102 dqs 6dqs 6 222 nc nc 43 nc dqs8 163 v ss v ss 103 dqs6 dqs6 223 v ss v ss 44 v ss v ss 164 nc cb6 104 v ss v ss 224 dq54 dq54 45 nc cb2 165 nc cb7 105 dq50 dq50 225 dq55 dq55 46 nc cb3 166 v ss v ss 106 dq51 dq51 226 v ss v ss 47 v ss v ss 167 nc nc 107 v ss v ss 227 dq60 dq60 front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 9 48 nc nc 168 reset reset 108 dq56 dq56 228 dq61 dq61 key key 109 dq57 dq57 229 v ss v ss 49 nc nc 169 cke1/nc cke1/nc 110 v ss v ss 230 dm7 dm7 50 cke0 cke0 170 v dd v dd 111 dqs 7dqs 7 231 nc nc 51 v dd v dd 171 nc nc 112 dqs7 dqs7 232 v ss v ss 52 ba2 ba2 172 nc nc 113 v ss v ss 233 dq62 dq62 53 nc nc 173 v dd v dd 114 dq58 dq58 234 dq63 dq63 54 v dd v dd 174 a12 a12 115 dq59 dq59 235 v ss v ss 55 all all 175 a9 a9 116 v ss v ss 236 v ddspd v ddspd 56 a7 2 a7 2 176 v dd v dd 117 sa0 sa0 237 sa1 sa1 57 v dd v dd 177 a8 2 a8 2 118 scl scl 238 sda sda 58 a5 2 a5 2 178 a6 2 a6 2 119 sa2 sa2 239 v ss v ss 59 a4 2 a4 2 179 v dd v dd 120 v tt v tt 240 v tt v tt 60 v dd v dd 180 a3 2 a3 2 front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 10 on dimm thermal sensor the ddr3 sdram dimm temperature is monitored by in tegrated thermal sensor. the integrated thermal sensor comply with jedec ?tse2002av, serial presence detect with temperature sensor?. connection of thermal sensor temperature-to-digital conversion performance parameter condition min typ max unit temperature sensor accuracy (grade b) active range, 75c < t a < 95c - 0.5 1.0 c monitor range, 40c < t a < 125c - 1.0 2.0 c -20c < t a < 125c - 2.0 3.0 c resolution 0.25 c event scl sda sa0 sa1 sa2 event scl sda sa0 sa1 sa2 spd with integrated ts b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 11 functional block diagram 1gb, 128mx64 modu le(1rank of x16) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm1 a0?a14 a0?a14: sdrams d0?d3 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d3 cas cas : sdrams d0?d3 cke0 cke: sdrams d0?d3 we we : sdrams d0?d3 cs cs cs ba0?ba2 ba0?ba2: sdrams d0?d3 dqs0 dqs1 dq15 i/o 15 v ss d0?d3 v dd /v dd q d0?d3 d0?d3 v ref dq notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs,dqs resistors;refer to asso- ciated topology diagram. 4. refer to the approp riate clock wiring topology under the dimm wiring details section of this document. 5. the pair ck1 and ck1# is terminated in 75ohm but is not used on the module. 6. a15 is not routed on the module. 7. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 8. one spd exists per module. scl wp spd v ddspd odt0 dqs 0 dqs 1 odt: sdrams d0?d3 s 0 ck0 ck: sdrams d0?d3 sa2 d0?d3 v ref ca a2 ck 0ck : sdrams d0?d3 ldqs ldqs ldm udqs udqs udm dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm2 i/o 4 i/o 5 i/o 6 i/o 7 dq28 dq29 dq30 dq24 dq25 dq26 dq27 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm3 cs dqs2 dqs3 dq31 i/o 15 dqs2 dqs3 ldqs ldqs ldm udqs udqs udm dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq40 dq41 dq42 dq43 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm5 cs cs cs dqs4 dqs5 dq47 i/o 15 dqs 4 dqs5 ldqs ldqs ldm udqs udqs udm dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq56 dq57 dq58 dq59 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm7 cs dqs6 dqs7 dq63 i/o 15 dqs6 dqs7 ldqs ldqs ldm udqs udqs udm reset reset :sdrams d0-d3 zq zq zq zq b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 12 2gb, 256mx64 modu le(1rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0?a15 a0?a15: sdrams d0?d7 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d7 cas cas : sdrams d0?d7 cke0 cke: sdrams d0?d7 we we : sdrams d0?d7 cs cs cs cs cs cs cs cs ba0?ba2 ba0?ba2: sdrams d0?d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs 2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 7 dqs dqs dqs dqs v ss d0?d7 v dd /v dd q d0?d7 d0?d7 v ref dq scl wp spd v ddspd odt0 dqs 0 dqs dqs dqs 4 dqs 1 dqs dqs dqs2 dqs dqs 3 dqs dqs 5 dqs 6 dqs dqs 7 dqs odt: sdrams d0?d7 s 0 ck0 ck: sdrams d0?d7 sa2 d0?d7 v ref ca a2 ck 0ck : sdrams d0?d7 zq zq zq zq zq zq zq zq reset reset : sdrams d0-d7 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs/dqs resistors;refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. refer to section 3.1 of this document for details on address mirroring. 6. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 7. one spd exists per module. b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 13 2gb, 256mx72 modu le(1rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0?a15 a0?a15: sdrams d0?d8 a0 spd(ts integrated) a1 sa0 sa1 sda ras ras : sdrams d0?d8 cas cas : sdrams d0?d8 cke0 cke: sdrams d0?d8 we we : sdrams d0?d8 s 0 cs cs cs cs cs cs cs cs ba0?ba2 ba0?ba2: sdrams d0?d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs 2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs8 dm8 dqs dqs dqs dqs dqs v ss d0?d8 v dd /v dd q d0?d8 d0?d8 v ref dq scl event spd v ddspd odt0 odt: sdrams d0?d8 dqs 0 dqs dqs dqs 4 dqs 1 dqs dqs dqs2 dqs dqs 3 dqs dqs 8 dqs dqs 5 dqs 6 dqs dqs 7 dqs ck0 ck: sdrams d0?d8 sa2 v ref ca d0?d8 a2 ck 0ck : sdrams d0?d8 zq zq zq zq zq zq zq zq zq reset reset : sdrams d0-d8 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s rela- tionships must be maintained as shown. 3. dq,cb,dm,dqs/dqs resistors;refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. for each dram, a unique zq resistor is connected to ground.the zq resis- tor is 240ohm+-1% 6. one spd exists per module. event b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 14 4gb, 512mx64 modu le(2rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 d9 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0?a15 a0-a15: sdrams d0?d15 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d15 cas cas : sdrams d0?d15 we we : sdrams d0?d15 s 0 s 1 cs cke1 cke: sdrams d8?d15 ba0?ba2 ba0?ba2: sdrams d0?d15 dqs0 dqs dqs4 dqs1 dqs5 dqs2 dqs3 dm6 dqs6 dqs7 dq15 i/o 7 i/o 7 v ss d0?d15 v dd /v dd q d0?d15 d0?d15 v ref dq scl wp spd v ddspd dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dqs 0 dqs 4 dqs 1 dqs 5 dqs 2 dqs 6 dqs 3 dqs 7 odt0 odt: sdrams d0?d7 odt1 odt: sdrams d8?d15 cke0 cke: sdrams d0?d7 ck0 ck: sdrams d0?d7 ck 0ck : sdrams d0?d7 sa2 d0?d15 v ref ca a2 ck1 ck: sdrams d8?d15 ck 1ck : sdrams d8?d15 zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq reset reset : sdrams d0-d3 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs,dqs resistors;refer to associated topo logy diagram. 4. refer to section 3.1 of this document for details on address mirroring. 5. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 6. one spd exists per module. b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 15 4gb, 512mx72 modu le(2rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 i/o 1 i/o 2 i/o 3 d0 d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 d10 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a0?a15 a0-a15: sdrams d0?d17 ras ras : sdrams d0?d17 cas cas : sdrams d0?d17 we we : sdrams d0?d17 cke1 cke: sdrams d9?d17 ba0?ba2 ba0-ba2: sdrams d0?d17 dq15 i/o 7 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 dm8 vss d0?d17 v dd /v dd q d0?d17 d0?d17 v ref dq spd v ddspd dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs i/o 0 i/o 0 dm0 dm4 s 0 s 1 dqs0 dqs4 dqs 0 dqs 4 dm1 dm5 dqs1 dqs5 dqs 1dqs 5 dm2 dqs2 dm6 dqs6 dqs 2 dm3 dm7 dqs3 dqs7 dqs 3 dqs 7 dqs 6 dqs 8 odt0 odt: sdrams d0?d8 odt1 odt: sdrams d9?d17 cke0 cke: sdrams d0?d8 ck0 ck: sdrams d0?d8 ck 0ck : sdrams d0?d8 d0?d17 v ref ca ck1 ck: sdrams d9?d17 ck 1ck : sdrams d9?d17 zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq reset reset : sdrams d0-d17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,cb,dm/dqs/dqs resistors;refer to associated topology diagram. 4. refer to section 3.1 of this document for details on addr ess mirroring. 5. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 6. one spd exists per module. a0 spd(ts integrated) a1 sa0 sa1 sda scl event sa2 a2 event b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 16 absolute maximum ratings absolute maximum dc ratings notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat - ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. dram component operat ing temperature range notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for mea - surement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur - ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refres h (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. hynix ddr3 sdrams support auto self-refresh and ex tended temperature range and please refer to hynix component datasheet and/or the di mm spd for trefi requirement in the extended temperature range. absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 1, vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 1, v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 o c1, 2 temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range 85 to 95 o c1,3 b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 17 ac & dc operating conditions recommended dc operating conditions notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters ar e measured with vdd and vddq tied together. ac & dc input measurement levels ac and dc logic input levels for single-ended signals ac and dc input levels for single -ended command and address signals notes: 1. for input only pins except reset , vref = vrefca (dc). 2. refer to ?overshoot and undershoot specifications? on page 30. 3. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. recommended dc operating conditions symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 single ended ac and dc input levels for command and address symbol parameter ddr3-800/1066/1333/1600 unit notes min max vih.ca(dc100) dc input logic high vref + 0.100 vdd v 1 vil.ca(dc100) dc input logic low vss vref - 0.100 v 1 vih.ca(ac175) ac input logic high vref + 0.175 note2 v 1, 2 vil.ca(ac175) ac input logic low note2 vref - 0.175 v 1, 2 vih.ca(ac150) ac input logic high vref + 0.150 note2 v 1, 2 vil.ca(ac150) ac input logic low note2 vref - 0.150 v 1, 2 v refca(dc ) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 18 ac and dc input levels for single-ended signals ddr3 sdram will support two vih/v il ac levels for ddr3-800 and ddr3-1066 as specified in the table below. ddr3 sdram will also support corresponding tds values (table 41 and table 47 in ?ddr3 device operation?) as well as derating tables in table 44 of ?ddr3 device operation? depending on vih/vil ac lev- els. notes: 1. vref = vrefdq (dc). 2. refer to ?overshoot and undershoot specifications? on page 30. 3. the ac peak noise on v ref may not allow v ref to deviate from v refdq(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. single ended ac and dc input levels for dq and dm symbol parameter ddr3-800/1066 ddr3-1333/1600 unit notes min max min max vih.ca(dc100) dc input logic high vref + 0.100 vdd vref + 0.100 vdd v 1 vil.ca(dc100) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1 vih.ca(ac175) ac input logic high vref + 0.175 note2 - - v 1, 2 vil.ca(ac175) ac input logic lo w note2 vref - 0.175 - - v 1, 2 vih.ca(ac150) ac input logic high vref + 0.150 note2 vref + 0.150 note2 v 1, 2 vil.ca(ac150) ac input logic low note2 vr ef - 0.150 note2 vref - 0.150 v 1, 2 v refdq(dc ) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4 b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 19 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vrefca and v refdq are illustrated in figure below. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in the table ?different ial input slew rate definition? on page 25. further- more v ref (t) may temporarily deviate from v ref (dc) by no more than +/- 1% vdd. illustration of v ref(dc) tolerance and v ref ac-noise limits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) , and v il(dc) are depen- dent on v ref . ?v ref ? shall be understood as v ref(dc) , as defined in figure above. this clarifies that dc-variations of v ref affect the absolute voltage a sign al has to reach to achieve a valid high or low level and therefore the time to which se tup and hold is measured. system timing and voltage budgets need to account for v ref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specific ation and derating values need to include time and voltage associated with v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the speci- fied limit (+/- 1% of vdd) are included in dram timings and their associated deratings. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t) b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 20 ac and dc logic input levels for differential signals differential signal definition definition of differential ac-swi ng and ?time above ac-level? t dvac time differential input voltage(i.e.dqs - dqs#, ck - ck#) v il.diff.ac.max v il.diff.max 0 v il.diff.min v il.diff.ac.min t dvac half cycle t dvac b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 21 differential swing requirem ents for clock (ck - ck ) and strobe (dqs-dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil (ac) of aadd/cmd and vrefca; for dqs - dqs , dqsl, dqsl , dqsu, dqsu use vih/vil (ac) of dqs and vrefdq; if a reduced ac-high or ac-low le vels is used for a signal group, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita - tions for overshoot and undershoot. refer to ?overshoot and unders hoot specifications? on page 30. differential ac and dc input levels symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vihdiff differential input high + 0.200 note 3 v 1 vildiff differential input logic low note 3 - 0.200 v 1 vihdiff (ac) differential input high ac 2 x (vih (ac) - vref) note 3 v 2 vildiff (ac) differential input low ac note 3 2 x (vil (ac) - vref) v 2 allowed time before ringback (tdvac) for ck - ck and dqs - dqs slew rate [v/ns] tdvac [ps] @ |vih/ldiff (ac)| = 350mv tdvac [ps] @ |vih/ldiff (ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 22 single-ended requirements for differential signals each individual component of a differen tial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , of dqsu ) has also to comply with certain requ irements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax (approximately equal to the ac-levels (vih (ac) / vil (ac)) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (a pproximately the ac-levels (vih (ac) / vil (ac)) for dq signals) in every half-cyc le preceding and following a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g., if vih.ca(ac150)/vil.ca(ac150) is used for add/cmd signal s, then these ac-levels apply also for the single- ended signals ck and ck . single-ended requirements for differential signals. note that, while add/cmd and dq signal requirements are with respect to vref, the single-ended compo- nents of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the transition of single-ended signals through the ac-lev els is used to measure se tup time. for single-ended components of differential signals the requirement to reach vselmax, vsehmin ha s no bearing on timing, but adds a restriction on the common mode characteristics of these signals. vdd or vddq vsehmin vdd/2 or vddq/2 vseh vselmax vss or vssq ck or dqs vsel time b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 23 notes: 1. for ck, ck use vih/vil (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use vih/vil (ac) of dqs. 2. vih (ac)/vil (ac) for dqs is based on vrefdq; vih (ac) /vil (ac) for add/cmd is based on vrefca; if a reduced ac-high or ac-low level is used for a signal gr oup, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita - tions for overshoot and undershoot. refer to ?overshoot and unders hoot specifications? on page 30. differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in table below. the differential input cross point voltage vix is measured from the actual cross point of true and complement signal s to the midlevel between of vdd and vss vix definition single-ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vseh single-ended high level for strobes (vdd / 2) + 0.175 note 3 v 1,2 single-ended high level for ck, ck (vdd /2) + 0.175 note 3 v 1,2 vsel single-ended low level for strobes note 3 (vdd / 2) = 0.175 v 1,2 single-ended low level for ck, ck note 3 (vdd / 2) = 0.175 v 1,2 vdd vss vdd/2 v ix v ix v ix ck , dqs ck, dqs b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 24 notes: 1. extended range for v ix is only allowed for clock and if sing le-ended clock input signals ck and ck are monotonic with a single-ended swing vsel / vseh of at least vdd/2 +/-250 mv, and when the differential slew rate of ck - ck is larger than 3 v/ns. 2. refer to the table ?single-ended levels for ck, dq s, dqsl, dqsu, ck, dqs, dqsl or dqsu? on page 23 for vsel and vseh standard values. slew rate definitions for single-ended input signals see 7.5 ?address / command setup, hold and derating ? on page 137 in ?ddr3 device operation? for sin- gle-ended slew rate definitions for address and command signals. see 7.6 ?data setup, hold and slew rate derating? on page 144 in ?ddr3 device operation? for single- ended slew rate definition for data signals. cross point voltage for differential input signals (ck, dqs) symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max v ix differential input cross point voltage relative to vdd/2 for ck, ck -150 150 mv -175 175 mv 1 v ix differential input cross point voltage relative to vdd/2 for dqs, dqs -150 150 mv b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 25 slew rate definitions for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measur ed as shown in table and figure below. notes: the differential signal (i.e. ck-ck and dqs-dqs ) must be linear between these thresholds. differential input slew rate definition for dqs, dqs and ck, ck differential input slew rate definition description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin [vihdiffmi n-vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax [vihdiffmi n-vildiffmax] / deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck# b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 26 ac & dc output measurement levels single ended ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of 0. 1 x v ddq is based on approximately 50% of the st atic single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq / 2. differential ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of 0.2 x v ddq is based on approximately 50% of the st atic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq /2 at each of the differential outputs. single-ended ac and dc output levels symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x v ddq v v oh(ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol(ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 differential ac and dc output levels symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x v ddq v1 v oldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x v ddq v1 b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 27 single ended ou tput slew rate when the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals are sh own in table and figure below. notes: 1. output slew rate is verified by design and charac terisation, and may not be su bject to production test. single ended output slew rate definition description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) -v ol(ac) ] / deltatrse single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) -v ol(ac) ] / deltatfse output slew rate (single-ended) ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units parameter symbol min max min max min max min max single-ended output slew rate srqse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns delta tfse delta trse voh(ac) vol(ac) v single ended output voltage(l.e.dq) single ended output slew rate definition b48614/178.104.2.80/2010-10-18 17:07
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 28 differential output slew rate with the reference load for timing measurements, output slew rate for falling an d rising edges is defined and measured between voldiff (ac) and vohdiff (ac) fo r differential signals as shown in table and figure below. differential output slew rate definition differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatrdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatfdiff notes: 1. output slew rate is verified by design and charac terization, and may not be subject to production test. differential output slew rate ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units parameter symbol min max min max min max min max differential output slew rate srqdiff 5 10 5 10 5 10 tbd 10 v/ns description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 29 reference load for ac timing and output slew rate figure below represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of an y particular system environment or a depiction of the actual load presented by a production tester. system de signers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transm ission lines terminated at the tester electronics. reference load for ac timing and output slew rate dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 30 overshoot and unders hoot specifications address and control overshoot and undershoot specifications address and control overshoot and undershoot definition ac overshoot/undershoot specification for address and control pins parameter ddr3- 800 ddr3- 1066 ddr3- 1333 ddr3- 1600 units maximum peak amplitude allowed for overshoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area. (see figure below) 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure below) 0.67 0.5 0.4 0.33 v-ns maximum undershoot area below vss (see figure below) 0.67 0.5 0.4 0.33 v-ns (a0-a15, ba0-ba3, cs , ras , cas , we , cke, odt) see figure below for each parameter definition maximum amplitude overshoot area vdd vss maxim um am plitude undershoot area time (ns) address and control overshoot and undershoot definition volts (v) b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 31 clock, data, strobe and mask over shoot and undershoot specifications clock, data, strobe and mask ov ershoot and undershoot definition ac overshoot/undershoot specificatio n for clock, data, strobe and mask parameter ddr3- 800 ddr3- 1066 ddr3- 1333 ddr3- 1600 units maximum peak amplitude allowed for overshoot area. (see figure below) 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure below) 0.25 0.19 0.15 0.13 v-ns maximum undershoot area below vss (see figure below) 0.25 0.19 0.15 0.13 v-ns (ck, ck , dq, dqs, dqs , dm) see figure below for each parameter definition maximum amplitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v) b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 32 refresh parameters by device density refresh parameters by device density parameter rtt_nom setting 512mb 1gb 2gb 4gb 8gb units notes ref command act or ref command time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 us 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 us b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 33 standard speed bins ddr3 sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see ?speed bin table notes? on page 37. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3 supported cl settings 6 n ck supported cwl settings 5 n ck b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 34 ddr3-1066 speed bins for specific notes see ?speed bin table notes? on page 37. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4, 5 cwl = 6 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 5 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3 supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 35 ddr3-1333 speed bins for specific notes see ?speed bin table notes? on page 37. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 8 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 8 ?ns pre command period t rp 13.5 (13.125) 8 ?ns act to act or ref command period t rc 49.5 (49.125) 8 ?ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2, 3,4, 6 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 6 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 6 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 6 reserved cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 6 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3 reserved ns supported cl settings 6, 8, (7), 9, (10) n ck supported cwl settings 5, 6, 7 n ck b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 36 ddr3-1600 speed bins for specific notes see ?speed bin table notes? on page 37. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 8 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 8 ?ns pre command period t rp 13.75 (13.125) 8 ?ns act to act or ref command period t rc 48.75 (48.125) 8 ?ns act to pre command period t ras 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 7 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 7 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 7 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 7 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1, 2, 3 supported cl settings 6, (7), 8, (9), 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 37 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1, the cl setting and cwl setting result in tck(av g).min and tck(avg).max requirements. when making a selection of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies ma y not be guaranteed. an application should use the next smaller jedec standard tck (avg) value (2.5, 1. 875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [ns] / tck (avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck (avg) = taa. max / clselected and round the resulting tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clse lected. 4. ?reserved? settings are not allowed. user must program a different value. 5. any ddr3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 6. any ddr3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1600 speed bin also supports functional oper ation at lower frequencie s as shown in the table which are not subject to production tests but verified by design/characterization. 8. hynix ddr3 sdram devices support down binning to cl=7 and cl=9, and taa/trcd/trp satisfy mini- mum value of 13.125ns. spd settings are also prog rammed to match. for example, ddr3 1333h devices supporting down binning to ddr3-1066f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). ddr3-1600k devices supporting down binning to ddr3-1333h or ddr3 1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trp- min (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be pro- grammed accordingly. for example, 49.125ns (trasm in + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 38 environmental parameters note : 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional operation at or above th e conditions indicated is not implied. expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. up to 9850 ft. 3. the component maximum case temperature ( t case ) shall not exceed the value specified in the ddr3 dram component specification. symbol parameter rating units notes t opr operating temperature (ambient) 0 to +55 o c3 h opr operating humidity (relative) 10 to 90 % t stg storage temperature -50 to +100 o c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1, 2 b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 39 pin capacitance (vdd=1.5v, vddq=1.5v) 1gb: hmt312u6bfr6c 2gb: hmt325u6bfr8c 2gb: hmt325u7bfr8c 4gb: hmt351u6bfr8c 4gb: hmt351u7bfr8c note: 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 40 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patt erns are defined. figure below (measurement setup and test load for idd an d iddq (optional) measurements) shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) ar e measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied togeth er. any iddq current is not included in idd cur - rents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied togeth er. any idd current is not included in iddq cur - rents. attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io powe r to actual io power as outlined in the figure below (correlation from simulated channel io powe r to actual channel io power supported by iddq measurement). in dram module application, iddq cannot be measured separately since vdd and vddq are using on merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patte rns are described in table 3 through table 10. ? idd measurements are done after properly initializi ng the ddr3 sdram. this includes but is not lim - ited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = { cs , ras , cas , we }:= {high, low, low, low} define d = { cs , ras , cas , we }:= {high, high, high, high} b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 41 measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above correlation from simulated channel io po wer to actual channel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 42 table 1 -timings used for idd an d iddq measurement-loop patterns table 2 -basic idd and id dq measurement conditions symbol ddr3-1066 ddr3-1333 ddr3-1600 unit 7-7-7 9-9-9 11-11-11 t ck 1.875 1.5 1.25 ns cl 7 9 11 nck n rcd 7911nck n rc 27 33 39 nck n ras 20 24 28 nck n rp 7911nck n faw 1kb page size 20 20 24 nck 2kb page size 27 30 32 nck n rrd 1kb page size 4 4 5 nck 2kb page size 6 5 6 nck n rfc -512mb 48 60 72 nck n rfc -1 gb 59 74 88 nck n rfc - 2 gb 86 107 128 nck n rfc - 4 gb 160 200 240 nck n rfc - 8 gb 187 234 280 nck symbol description i dd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partiall y toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cycl ing with one bank active at a time: 0,0,1,1,2,2,... (see table 3); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3. i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, n rc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, da ta io: partially toggling ac cording to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4. b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 43 i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pr echarge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 symbol description b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 44 i dd4r operating burst read current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling according to tabl e 7; data io: seamless read data burst with different data between one burst and the next one according to tabl e 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling according to tabl e 8; data io: seamless read data burst with different data between one burst and the next one according to tabl e 8; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see table 8); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high ; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partiall y toggling according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6et self-refresh current: extended temperature range t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6tc auto self-refresh current t case : 0 - 95 o c; auto self-refresh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: auto self-r efresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 45 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a),f) ; al: cl-1; cs : high between act and rda; command, address, bank a ddress inputs: partially togg ling according to table 10; data io: read data burst with different data betw een one burst and the next one according to table 10; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,...7) with different address- ing, wee table 10; output buffer an d rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 46 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act0011000000 00 - 1,2 d, d1000000000 00 - 3,4 d , d 1111000000 00 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre0010000000 00 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111000000 f0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 47 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid- level. b) burst sequence driven on each dq signal by re ad command. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nr c - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,. ..4 until nrc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1, ...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1, ...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 48 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d 10000000000 - 1 d 10000000000 - 2d 111100000f0 - 3d 111100000f0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7 b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 49 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 50 table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary. b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 51 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2 d 1 0 0 0 0 0 00 0 0 0 0 - ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d 1 0 0 0 0 3 00 0 0 f 0 - assert and repeat abov e d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 f 0 - assert and repeat abov e d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d 1 0 0 0 0 0 00 0 0 f 0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d 1 0 0 0 0 1 00 0 0 0 0 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d 1 0 0 0 0 3 00 0 0 0 0 - assert and repeat abov e d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 0 0 - assert and repeat abov e d command until 4* nfaw - 1, if necessary b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 52 idd specifications (tcase: 0 to 95 o c) * module idd values in the datasheet are only a calculation based on the component idd spec. the actual measurements may vary according to dq loading cap. 1gb, 128m x 64 u-di mm: hmt312u6bfr6c 2gb, 256m x 64 u-di mm: hmt325u6bfr8c symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 240 260 260 ma idd1 280 300 300 ma idd2n 100 120 120 ma idd2nt 140 160 180 ma idd2p0 48 48 48 ma idd2p1 60 60 60 ma idd2q 100 120 120 ma idd3n 120 140 160 ma idd3p 60 60 60 ma idd4r 420 520 560 ma idd4w 420 520 600 ma idd5b 660 680 680 ma idd6 48 48 48 ma idd6et 60 60 60 ma idd6tc 60 60 60 ma idd7 520 680 720 ma symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 360 400 440 ma idd1 440 480 520 ma idd2n 200 240 240 ma idd2nt 256 280 320 ma idd2p0 96 96 96 ma idd2p1 120 120 120 ma idd2q 200 240 240 ma idd3n 240 280 320 ma idd3p 120 120 120 ma idd4r 640 760 840 ma idd4w 640 760 880 ma idd5b 1200 1240 1280 ma idd6 96 96 96 ma idd6et 120 120 120 ma idd6tc 120 120 120 ma idd7 880 1080 1160 ma b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 53 2gb, 256m x 72 u-di mm: hmt325u7bfr8c 4gb, 512m x 64 u-di mm: hmt351u6bfr8c symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 405 450 495 ma idd1 495 540 585 ma idd2n 225 270 270 ma idd2nt 288 315 360 ma idd2p0 108 108 108 ma idd2p1 135 135 135 ma idd2q 225 270 270 ma idd3n 270 315 360 ma idd3p 135 135 135 ma idd4r 720 855 945 ma idd4w 720 855 990 ma idd5b 1350 1395 1440 ma idd6 108 108 108 ma idd6et 135 135 135 ma idd6tc 135 135 135 ma idd7 990 1215 1305 ma symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 560 640 760 ma idd1 640 720 840 ma idd2n 400 480 480 ma idd2nt 512 560 640 ma idd2p0 192 192 192 ma idd2p1 240 240 240 ma idd2q 400 480 480 ma idd3n 480 560 640 ma idd3p 240 240 240 ma idd4r 840 1000 1160 ma idd4w 840 1000 1200 ma idd5b 1400 1480 1600 ma idd6 192 192 192 ma iddet 240 240 240 ma idd6tc 240 240 240 ma idd7 1080 1320 1480 ma b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 54 4gb, 512m x 72 u-di mm: hmt351u7bfr8c symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 630 720 855 ma idd1 720 810 945 ma idd2n 450 540 540 ma idd2nt 576 630 720 ma idd2p0 216 216 216 ma idd2p1 270 270 270 ma idd2q 450 540 540 ma idd3n 540 630 720 ma idd3p 270 270 270 ma idd4r 945 1125 1305 ma idd4w 945 1125 1350 ma idd5b 1575 1665 1800 ma idd6 216 216 216 ma iddet 270 270 270 ma idd6tc 270 270 270 ma idd7 1215 1485 1665 ma b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 55 module dimensions 128mx64 - hmt312u6bfr6c 9.50 30.0 0 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 1.50 0.10 2.50 full r detail - a 1.27 0.10 3.18 front back side spd note : 1. tolerance on all dimensions unless otherwise stated. 0.13 units: millimeters b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 56 256mx64 - hmt325u6bfr8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 1.50 0.10 2.50 full r detail - a 1.27 0.10 3.18 back side 30.00 front spd note : 1. tolerance on all dimensions unless otherwise stated. 0.13 units: millimeters b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 57 256mx72 - hmt325u7bfr8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 1.50 0.10 2.50 full r detail - a 1.27 0.10 3.18 back side 30.00 front spd note : 1. tolerance on all dimensions unless otherwise stated. 0.13 units: millimeters b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 58 512mx64 - hmt351u6bfr8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 1.50 0.10 2.50 full r detail - a 1.27 0.10 4.00 back side 30.00 front spd note : 1. tolerance on all dimensions unless otherwise stated. 0.13 units: millimeters b48614/178.104.2.80/2010-10-18 17:08
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.0 / oct. 2010 59 512mx72 - hmt351u7bfr8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 1.50 0.10 2.50 full r detail - a 1.27 0.10 4.00 back side 30.00 front spd note : 1. tolerance on all dimensions unless otherwise stated. 0.13 units: millimeters b48614/178.104.2.80/2010-10-18 17:08

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